Conferences and Workshops

• Sylvain Girbal, Olivier Temam, Sami Yehia, Hugues Berry, and Zheng LI, " A memory interface for multi-purpose multi-stream accelerators,” ACM International conference on Compilers, architectures and synthesis for embedded systems (CASES), October 2010. (pdf)
• Dominik Auras, Sylvain Girbal, Hugues Berry, Olivier Temam and Sami Yehia, " CMA: Chip multi-accelerator," IEEE 8th Symposium on Application Specific Processors (SASP), June 2010. (pdf)
• Sami Yehia, Sylvain Girbal, Hugues Berry, and Olivier Temam, "Reconciling Specialization and Flexibility Through Compound Circuits," International Symposium on High-Performance Computer Architecture (HPCA), February 2009. (pdf)
• Nathan Clark, Amir Hormati, Scott Mahlke, Sami Yehia, and Krisztian Flautner, "Liquid SIMD: Abstracting SIMD Hardware Using Lightweight Dynamic Mapping," International Symposium on High-Performance Computer Architecture (HPCA), February 2007.(pdf)
• Nathan Clark, Amir Hormati, Scott Mahlke, and Sami Yehia, "Scalable Subgraph Mapping for Acyclic Computation Accelerators," International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2006. (pdf)
• Sami Yehia, Nathan Clark, Scott Mahlke, and Krisztian Flautner, "Exploring the Design Space of LUT-based Transparent Accelerators," International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005. (Best Paper Award). (pdf)
  
• Jean-Francois Collard, Norm Jouppi and Sami Yehia, "System-Wide Performance Monitors and their Application to the Optimization of Coherent Memory Accesses," ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP), June 2005. (pdf)
• Sami Yehia and Olivier Temam, "From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation," 31th Annual International Symposium on Computer Architecture (ISCA), June 2004. (pdf)
• Sami Yehia, Jean-François Collard and Olivier Temam, "Load Squared: Adding Logic Close to Memory to Reduce the Latency of Indirect Loads with High Miss Ratios," MEDEA Workshop, held in conjunction with the International Conference of Parallel Architectures and Compilation Techniques (PACT), October 2004. (pdf)
• Sami Yehia and Olivier Temam, "From Sequences of Dependent Instructions to Functions: A Complexity Effective Approach for Improving Performance without ILP or Speculation,,"Workshop on Complexity-effective Design (WCED) held in conjunction with the 30th Annual International Symposium on Computer Architecture (ISCA), June 2003. (pdf)
• Sami Yehia and Yasser Y. Hanafy, " Optimal Module Selection and Scheduling of Dynamically Reconfigurable Processors, 9th International Conference on Computer Theory and applications (ICCTA' 99), 1999, Alexandria, Egypt.

Journal Papers

• Arnaud Grasset, Philippe Millet, Philippe Bonnot, Sami Yehia, Wolfram Putzke-Roeming, Fabio Campi, Alberto Rosti, Michael Huebner, Nikolaos S. Voros and Davide Rossi,"The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform ," International Journal of Parallel Programming. (IJPP), Volume 38, 2010.
• Sami Yehia, Jean-François Collard and Olivier Temam, "Load Squared: Adding Logic Close to Memory to Reduce the Latency of Indirect Loads in Embedded and General Systems," Journal of Embedded  Computing (JEC) , Volume 2, Number 1, January 2006, IOS Press.

Other posters and talks

• Majed Chatti, Sami Yehia, Claude Timsit, Soraya Zertal, " A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications," Poster paper, International Conference on High Performance Computing and Simulation (HPCS), June 2010
• Marios Kleanthous, Sami Yehia, Yiannakis Sazeides, Emre Ozer, "A Replacement Policy Based on Dynamic Profiling and Hashed Information," Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), July 2007. (pdf)
• Philippe Bonnot, Sami Yehia, Arnaud Grasset, Eric Lenormand, Gilbert Edelin, "Mapping high performance and mission-critical applications to Embedded Architectures," 4th HiPEAC Industrial Workshop on Compilers and Architectures, November 2007. (pdf)

HiPEAC Roadmap

• Marc Duranton, Sami Yehia, Bjorn De Sutter, Koen De Bosschere, Albert Cohen, Babak Falsafi, Georgi Gaydadjiev, Manolis Katevenis, Jonas Maebe, Harm Munk, Nacho Navarro, Alex Ramirez, Olivier Temam, Mateo Valero, "The HiPEAC Vision, " 2012-2020 Roadmap of the FP7 Network of Excellence on High Performance and Embedded Architecture and Compilation, January 2010 (pdf)

PhD Thesis

• Ph.D. in Computer Science, Computer Architecture, Paris-Sud (Paris XI) University, Orsay, France.
• Ph.D. Thesis Title: “Alternative Approaches to Improve Performance without ILP”
• Defense Jury: André SEZNEC (IRISA/INRIA), Sanjay PATEL (University of Illinois at UrbanaChampaign),  Marc DURANTON (Philips Research) and Olivier TEMAM ( Paris-Sud XI University).
• September 2004, Advisor: Professor Olivier Temam.
• Dissertation    ps    ps.gz     pdf     pdf.gz

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